1. Field of the Invention
The present invention relates generally to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming a gate capable of improving refresh characteristics.
2. Description of the Prior Art
In general, a gate insulating layer of a MOSFET device is made from a silicon oxide layer (hereinafter, referred to as a SiO2 layer) obtained through terminal oxidation. As semiconductor devices have become highly integrated, the thickness of the gate oxide layer has been gradually reduced, but the density of impurities implanted into a channel and a source/drain junction area has gradually increased. Accordingly, the direct tunneling and boron penetration phenomenon may occur through the gate oxide layer having the reduced thickness and the leakage current of the semiconductor device may increase.
In particular, the leakage current of the semiconductor device mainly occurs at an edge portion of the channel subject to a high electric field, that is, at an overlap area between the gate and the source/drain junction area. If the leakage current of the semiconductor device increases, the refresh time for the semiconductor device is reduced.
Hereinafter, a conventional method of manufacturing a semiconductor device and problems thereof will be described with reference to FIG. 1.
Referring to FIG. 1, a gate oxide layer 3, a polysilicon layer 4, a metal silicide layer 5 and a hard mask layer 6 are sequentially formed on a semiconductor substrate 1 having an isolation layer 2 for defining an active area. Then, a gate 7 is formed by patterning the above layers 6, 5, 4 and 3. After that, spacers 8 are formed at both sidewalls of the gate 7. Then, a source/drain area 9 is formed on either side of the gate 7 (shown with dotted lines in FIG. 1) on an upper surface of the semiconductor substrate 1 corresponding to the spacers 8 formed at the sidewalls of the gate 7, thereby obtaining a transistor.
According to the above conventional method, the gate oxide layer 3 has a uniform thickness. Thus, if the thickness of the gate oxide layer 3 is reduced in order to improve the dielectric constant of the gate oxide layer 3 corresponding to the high integration of the semiconductor device, current leakage, such as gate induced drain leakage (GIDL), may occur at the edge portion of the channel, that is, at the overlap area between the gate oxide layer and the source/drain area, so that the refresh time of the semiconductor device is reduced.